Abstract
DAQ (Data AcQuisition) Systems for portable applications are mostly battery driven devices which underlie strong restrictions concerning the data rate due to the limited energy resources. In this article we present an effective DMA-based (Direct Memory Access) concept for data acquisition maintaining substantial computational power for e. g. online digital signal processing and wireless IEEE 802.15.4 based communication. Implemented on the Ultra-Low-Power Microcontroller MSP430 sample rates up to 96 kHz have been realised for single channel DAQ. The development was done within the project ‘intelligent Sensor and Actuator Network for Life science Application’ (iSANLA).
1 Introduction
In the framework of our development of an intelligent sensor and actuator network for life science application (iSANLA) a small battery driven sensor node has been designed. This sensor node (iNODE, intelligent Network Operating DEvice) includes analog electronics for signal conditioning and pre-processing as well as a TI MSP430 microcontroller [1] with internal and external peripheral devices for further processing of digital information. In further development stages several iNODEs will form a self configuring and self organising network [2].
Our developments are driven by two fields of applications. In the first field, neurological rehabilitation and sleep research, our starting goal is the long term monitoring of vegetative locomotor coordination. This requires multi-sensoric data acquisition, such as ECG, respiration and kinematical patterns of movements. A data rate below 512Hz will fit with these applications. In the second field, neurophysiology, our first goal is to monitor the dynamics of neuronal space specific information processing in freely behaving animals. The signal-bandwith of interest is approximately 5 kHz demanding a sample-frequency of ~16 kHz for a meaningful analysis of the signals. The outstanding attention of all instrumentation lies in the lossless collection of all measured data for the scientific evaluation. For the sake of online monitoring and real time feedback control application specific algorithms have to be applied in parallel to the recordings. Besides the usage of a restricted microcontroller system this requires the effective and flexible integration of existing technologies. Below, we will describe the optimised hardware and software concept for single channel data acquisition which fulfils these requirements.
2 Methods
The central component of the system is the Ultra-Low-Power microcontroller (μC) MSP430 with a 16 Bit RISC CPU. The applied derivative F1611 includes considerably internal peripheral components such as e.g. 10kB static RAM, 48kB Flash Memory, 12 Bit ADC with 8 Channels, 3 Channel DMA, 2 USART communication modules with SPI, I2C and UART. Presently the CPU can be driven with up to 8MHz. The power consumption of the CPU is 330μA @ 1 MIPS and 1.1μA in standby mode [1]. The μC is connected via the SPI interface to a mass storage device (SanDisk iNAND), which presently contains up to 4GB memory capacity. This device is compatible with the SecureDigital Card (SD flash memory) standard and features with PCB dimensions and low power consumption in comparisons with other memory concepts. The incoming analog signal is transformed according to the application and the ADC voltage range by digital controlled analog preprocessing electronics.
Acquired data will be stored in the SD-flash memory and may be processed in the memory of the μC. An optional data transfer using a communication interface to a Personal Computer or to an integrated IEEE 802.15.4 (ZigBee) RF-Transducer component to other sensor nodes is implemented [3]. Additionally all sensor nodes have an adaptive power management, which e.g. adjusts the driving CPU voltage concerning to the chosen CPU-clock frequency. Object orientated Embedded C++ was chosen to code the μC; therewith a complete and adjustable mapping of the hardware components to software objects has been achieved providing a functional encapsulation of the external peripherals.
Fig. 1: Block diagram of the DMA-based dataflow
The DMA based dataflow is shown in Fig. 2. The TimerA of the μC determines the sample frequency by triggering the ADC. The TimerA itself is driven by internal or external oscillators and may divide those incoming frequencies by a factor from 21 to 215. This allows to adjust a wide band of sample frequencies in combination with the choice of the frequency source (LF Crystal = 32.768 KHz, DCO <5 MHz or HF Crystal <=8 MHz). After the ADC sample and hold procedure a digital value is stored in an internal register of the ADC. This triggers the DMA channel 0 to transfer this value into the internal RAM of the μC. For this reason a memory block is allocated as a double buffer where each buffer can catch 256 Samples with 16 Bit. This matches the block size of the SD flash memory of 512 Bytes.
Once one buffer is filled, the DMA triggers an interrupt service routine ( ISR) which directs the incoming dataflow to the second buffer. Additionally the data transfer from the previous buffer to the SD flash memory will be initialised and started by configuring the DMA channel 1 and linking it to the SPI interface. The cyclic repetition of the sequence (in the following called ‘frame’) guarantees a continuously lossless data acquisition.
Andreas Schnitzer, Carmen Silex, Hong Ying, Michael Schiek
Zentralinstitut für Elektronik, ZEL, Forschungszentrum Jülich, Germany
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